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docs/기초실습/1.LEDONOFF.md
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# LED ON OFF
실습키트의 LED 16비트를 ONOFF하는 과정을 실습니다.
해당 값에 대한 비트에 LED 가 ON OFF되는지 확인한다.
![내 사진](imgs/led16.png)
## PIN 테이블
| 핀 번호 | 신호 |
|---------|------|
| PIN_B3 | LED_A[7] |
| PIN_B4 | LED_A[6] |
| PIN_B5 | LED_A[5] |
| PIN_B6 | LED_A[4] |
| PIN_B7 | LED_A[3] |
| PIN_B8 | LED_A[2] |
| PIN_B9 | LED_A[1] |
| PIN_B10 | LED_A[0] |
| PIN_B13 | LED_B[7] |
| PIN_B14 | LED_B[6] |
| PIN_B15 | LED_B[5] |
| PIN_B16 | LED_B[4] |
| PIN_B17 | LED_B[3] |
| PIN_B18 | LED_B[2] |
| PIN_B19 | LED_B[1] |
| PIN_B20 | LED_B[0] |
## VHDL 코드
```vhdl
library ieee;
use ieee.std_logic_1164.all;
entity led_test is
port( LED_A : out std_logic_vector(7 downto 0);
LED_B : out std_logic_vector(7 downto 0) );
end led_test;
architecture button_design of led_test is
begin
LED_A <= x"F0";
LED_B <= x"0F";
end button_design;
```
docs/기초실습/2.IN_OUT.md
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# IN_OUT
실습키트의 LED 16비트를 ONOFF하는 과정을 실습니다.
해당 값에 대한 비트에 LED 가 ON OFF되는지 확인한다.
![내 사진](imgs/in_out.png)
## PIN 테이블
| 핀 번호 | 신호 |
|---------|------|
| PIN_P21 | din[7] |
| PIN_N21 | din[6] |
| PIN_M21 | din[5] |
| PIN_L21 | din[4] |
| PIN_K21 | din[3] |
| PIN_J21 | din[2] |
| PIN_H21 | din[1] |
| PIN_F21 | din[0] |
| PIN_B3 | dout[7] |
| PIN_B4 | dout[6] |
| PIN_B5 | dout[5] |
| PIN_B6 | dout[4] |
| PIN_B7 | dout[3] |
| PIN_B8 | dout[2] |
| PIN_B9 | dout[1] |
| PIN_B10 | dout[0] |
## VHDL 코드
```vhdl
library ieee;
use ieee.std_logic_1164.all;
entity in_out is
port(
din : in std_logic_vector(7 downto 0); -- 8비트 입력
dout : out std_logic_vector(7 downto 0) -- 8비트 출력
);
end entity;
architecture rtl of in_out is
begin
-- 입력을 그대로 출력으로 전달
dout <= din;
end architecture;
```
docs/기초실습/3.CLK.md
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# CLK
실습키트의 50MHz의 클럭을 받아서 원하는 시간으로 LED ON OFF 과정을 수행한다.
코어모듈에 적용된 LED 와 CLK 오실레이터의 입력을 사용한다.
![내 사진](imgs/fpga_core.png)
## PIN 테이블
| 핀 번호 | 신호 |
|---------|------|
| PIN_T2 | clk |
| PIN_E4 | led |
## VHDL 코드
```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk is
port (
clk : in std_logic; -- PIN T2, 50MHz
led : out std_logic -- PIN E4 (active-high 가정)
);
end entity;
architecture rtl of clk is
signal cnt : integer range 0 to 49_999_999 := 0;
signal q : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if cnt = 49_999_999 / 5 then
cnt <= 0;
q <= not q; -- 1초마다 토글 (ON 1초, OFF 1초)
else
cnt <= cnt + 1;
end if;
end if;
end process;
led <= q; -- 보드가 active-low LED라면: led0 <= not q;
end architecture;
```
docs/기초실습/4.7SEG.md
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# 7SEG
실습키트의 7SEGMENT의 출력이 정상적으로 되는지 확인한다.
![내 사진](imgs/seg.png)
## PIN 테이블
| 핀 번호 | 신호 |
|---------|------|
| PIN_AA13 | led_out[0] |
| PIN_AA14 | led_out[1] |
| PIN_AA15 | led_out[2] |
| PIN_AA16 | led_out[3] |
| PIN_AA17 | led_out[4] |
| PIN_AA18 | led_out[5] |
| PIN_AA19 | led_out[6] |
| PIN_AA20 | led_out[7] |
| PIN_AB14 | seg[6] |
| PIN_AB15 | seg[5] |
| PIN_AB16 | seg[4] |
| PIN_AB17 | seg[3] |
| PIN_AB18 | seg[2] |
| PIN_AB19 | seg[1] |
| PIN_AB20 | seg[0] |
## VHDL 코드
```vhdl
library ieee;
use ieee.std_logic_1164.all;
entity seg_out is
port(
seg : out std_logic_vector(6 downto 0); -- 7-세그 출력 (g~a)
led_out : out std_logic_vector(0 to 7) -- 기존 인덱스(0 to 7)
);
end seg_out;
architecture SegmentDecoder of seg_out is
signal key : integer range 0 to 15 := 5; -- 표시할 숫자 (0~15)
begin
----------------------------------------------------------------
-- with-select: key 값 → seg 패턴 매핑 (VHDL-93 호환)
----------------------------------------------------------------
with key select
seg <=
"100" & "0000" when 0, -- 0
"111" & "1001" when 1, -- 1
"010" & "0100" when 2, -- 2
"011" & "0000" when 3, -- 3
"001" & "1001" when 4, -- 4
"001" & "0010" when 5, -- 5
"000" & "0010" when 6, -- 6
"111" & "1000" when 7, -- 7
"000" & "0000" when 8, -- 8
"001" & "0000" when 9, -- 9
"000" & "1000" when 10, -- A
"000" & "0011" when 11, -- b
"100" & "0110" when 12, -- C
"010" & "0001" when 13, -- d
"000" & "0110" when 14, -- E
"000" & "1110" when 15, -- F
"111" & "1111" when others; -- blank
----------------------------------------------------------------
-- LED 개별 비트 설정: 기존 코드 그대로 유지
----------------------------------------------------------------
led_out(7) <= '1'; -- LED 7번 ON
led_out(6) <= '1';
led_out(5) <= '1';
led_out(4) <= '0'; -- LED 4번 ON
led_out(3) <= '0';
led_out(2) <= '0';
led_out(1) <= '1';
led_out(0) <= '1'; -- LED 0번 ON
end architecture;
```
---
docs/기초실습/5.KEY_7SEG.md
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# KEY IN 7SEG
실습키트의 키의 입력을 받아, 7SEGMENT으로 출력, 출력이 정상적으로 되는지 확인한다.
<div class="image-row">
<div class="image-box">
<img src="../imgs/key_in.png">
<div><b>Keypad</b></div>
</div>
<div class="image-box">
<img src="../imgs/seg.png">
<div><b>7-Segment</b></div>
</div>
</div>
## PIN 테이블
| 핀 번호 | 신호 |
|---------|------|
| PIN_AA13 | led_out[0] |
| PIN_AA14 | led_out[1] |
| PIN_AA15 | led_out[2] |
| PIN_AA16 | led_out[3] |
| PIN_AA17 | led_out[4] |
| PIN_AA18 | led_out[5] |
| PIN_AA19 | led_out[6] |
| PIN_AA20 | led_out[7] |
| PIN_AB14 | seg[6] |
| PIN_AB15 | seg[5] |
| PIN_AB16 | seg[4] |
| PIN_AB17 | seg[3] |
| PIN_AB18 | seg[2] |
| PIN_AB19 | seg[1] |
| PIN_AB20 | seg[0] |
## VHDL 코드
```vhdl
library ieee;
use ieee.std_logic_1164.all;
entity seg_out is
port(
seg : out std_logic_vector(6 downto 0); -- 7-세그 출력 (g~a)
led_out : out std_logic_vector(0 to 7) -- 기존 인덱스(0 to 7)
);
end seg_out;
architecture SegmentDecoder of seg_out is
signal key : integer range 0 to 15 := 5; -- 표시할 숫자 (0~15)
begin
----------------------------------------------------------------
-- with-select: key 값 → seg 패턴 매핑 (VHDL-93 호환)
----------------------------------------------------------------
with key select
seg <=
"100" & "0000" when 0, -- 0
"111" & "1001" when 1, -- 1
"010" & "0100" when 2, -- 2
"011" & "0000" when 3, -- 3
"001" & "1001" when 4, -- 4
"001" & "0010" when 5, -- 5
"000" & "0010" when 6, -- 6
"111" & "1000" when 7, -- 7
"000" & "0000" when 8, -- 8
"001" & "0000" when 9, -- 9
"000" & "1000" when 10, -- A
"000" & "0011" when 11, -- b
"100" & "0110" when 12, -- C
"010" & "0001" when 13, -- d
"000" & "0110" when 14, -- E
"000" & "1110" when 15, -- F
"111" & "1111" when others; -- blank
----------------------------------------------------------------
-- LED 개별 비트 설정: 기존 코드 그대로 유지
----------------------------------------------------------------
led_out(7) <= '1'; -- LED 7번 ON
led_out(6) <= '1';
led_out(5) <= '1';
led_out(4) <= '0'; -- LED 4번 ON
led_out(3) <= '0';
led_out(2) <= '0';
led_out(1) <= '1';
led_out(0) <= '1'; -- LED 0번 ON
end architecture;
```
---
docs/기초실습/6.CLK_7SEG.md
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# CLK AT 7SEG
CLK을 입력받아. 7SEGMENT 값들이 증가되어 출력되도록 한다.
![내 사진](imgs/seg.png)
---
## PIN 테이블
| 핀 번호 | 신호 |
|---------|------|
| PIN_AA13 | led_out[0] |
| PIN_AA14 | led_out[1] |
| PIN_AA15 | led_out[2] |
| PIN_AA16 | led_out[3] |
| PIN_AA17 | led_out[4] |
| PIN_AA18 | led_out[5] |
| PIN_AA19 | led_out[6] |
| PIN_AA20 | led_out[7] |
| PIN_AB14 | seg[6] |
| PIN_AB15 | seg[5] |
| PIN_AB16 | seg[4] |
| PIN_AB17 | seg[3] |
| PIN_AB18 | seg[2] |
| PIN_AB19 | seg[1] |
| PIN_AB20 | seg[0] |
| PIN_T2 | clk |
---
## VHDL 코드
```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- 정수형 연산용
entity seg_clk is
port(
clk : in std_logic; -- 50MHz 클럭 입력
led_out : out std_logic_vector(0 to 7); -- LED 출력
seg : out std_logic_vector(6 downto 0) -- 7세그 출력
);
end entity;
architecture rtl of seg_clk is
----------------------------------------------------------------
-- 신호 선언
----------------------------------------------------------------
signal cnt : unsigned(25 downto 0) := (others => '0'); -- 50MHz → 1Hz 분주용
signal sec_tick : std_logic := '0'; -- 1초 펄스
signal num : unsigned(3 downto 0) := (others => '0'); -- 0~15 카운트
begin
----------------------------------------------------------------
-- 50MHz → 1Hz 분주기 (1초마다 sec_tick='1')
----------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if cnt = 49_999_999 then -- 50,000,000 - 1
cnt <= (others => '0');
sec_tick <= '1';
else
cnt <= cnt + 1;
sec_tick <= '0';
end if;
end if;
end process;
----------------------------------------------------------------
-- 초당 1회 숫자 증가 (0~15 순환)
----------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if sec_tick = '1' then
if num = 15 then
num <= (others => '0');
else
num <= num + 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------
-- 숫자 → 7세그 변환
----------------------------------------------------------------
with num select
seg <=
("100" & "0000") when "0000", -- 0
("111" & "1001") when "0001", -- 1
("010" & "0100") when "0010", -- 2
("011" & "0000") when "0011", -- 3
("001" & "1001") when "0100", -- 4
("001" & "0010") when "0101", -- 5
("000" & "0010") when "0110", -- 6
("111" & "1000") when "0111", -- 7
("000" & "0000") when "1000", -- 8
("001" & "0000") when "1001", -- 9
("000" & "1000") when "1010", -- A
("000" & "0011") when "1011", -- b
("100" & "0110") when "1100", -- C
("010" & "0001") when "1101", -- d
("000" & "0110") when "1110", -- E
("000" & "1110") when "1111", -- F
("111" & "1111") when others; -- blank
----------------------------------------------------------------
-- LED 출력 (기존 그대로 유지)
----------------------------------------------------------------
led_out(7) <= '1';
led_out(6) <= '0';
led_out(5) <= '0';
led_out(4) <= '0';
led_out(3) <= '0';
led_out(2) <= '0';
led_out(1) <= '0';
led_out(0) <= '1';
end architecture;
```
---
docs/기초실습/7.MODE_SW.md
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# MODE SWITCH
슬라이드 스위치를 이용한 모드 설정에 사용한다.
해당 슬라이드를 입력으로 설정하여 입력되는 값들을 사용한다.
![내 사진](imgs/modesw.png)
---
## PIN 테이블
| 핀 번호 | 신호 |
|---------|------|
| PIN_B3 | dout[1] |
| PIN_B4 | dout[0] |
| PIN_M2 | din[1] |
| PIN_J2 | din[0] |
---
## VHDL 코드
```vhdl
library ieee;
use ieee.std_logic_1164.all;
entity modsw is
port (
din : in std_logic_vector(1 downto 0); -- 8bit 입력
dout : out std_logic_vector(1 downto 0) -- 8bit 출력
);
end modsw;
architecture rtl of modsw is
begin
dout <= din; -- 입력을 그대로 출력
end rtl;
```
---
docs/기초실습/files/README.txt
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사용법
1. ASM을 HEX로 변환
python asmtohex.py led.asm
결과:
led.hex
2. HEX를 COM3로 전송
python hexsend.py led.hex
pyserial 설치:
pip install pyserial
명령어 포맷:
16bit = opcode[15:12] + operand[11:0]
명령어:
NOP 0x0
LOAD n 0x1
INC 0x2
DEC 0x3
JMP addr 0x4
JZ addr 0x5
JNZ addr 0x6
LED_ON 0x7
LED_OFF 0x8
DELAY n 0x9
led.asm 변환 결과:
1005
7000
9064
8000
9064
3000
6001
5008
7000
4008
시리얼 전송 바이트:
10 05 70 00 90 64 80 00 90 64 30 00 60 01 50 08 70 00 40 08
docs/기초실습/files/asmtohex.py
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#!/usr/bin/env python3
import sys
from pathlib import Path
OPCODE = {
"NOP": 0x0,
"LOAD": 0x1,
"INC": 0x2,
"DEC": 0x3,
"JMP": 0x4,
"JZ": 0x5,
"JNZ": 0x6,
"LED_ON": 0x7,
"LED_OFF": 0x8,
"DELAY": 0x9,
}
def remove_comment(line):
return line.split(";")[0].strip()
def parse_number(text):
text = text.strip()
if text.lower().startswith("0x"):
return int(text, 16)
if text.lower().startswith("0b"):
return int(text, 2)
return int(text, 10)
def assemble(asm_text):
labels = {}
instructions = []
pc = 0
# 1차 패스: 라벨 주소 수집
for raw_line in asm_text.splitlines():
line = remove_comment(raw_line)
if not line:
continue
if line.endswith(":"):
label = line[:-1].strip()
if label in labels:
raise ValueError(f"중복 라벨: {label}")
labels[label] = pc
continue
if ":" in line:
label_part, inst_part = line.split(":", 1)
label = label_part.strip()
inst_line = inst_part.strip()
if label in labels:
raise ValueError(f"중복 라벨: {label}")
labels[label] = pc
if inst_line:
instructions.append(inst_line)
pc += 1
continue
instructions.append(line)
pc += 1
machine = []
# 2차 패스: 명령어 변환
for addr, line in enumerate(instructions):
parts = line.replace(",", " ").split()
if not parts:
continue
mnemonic = parts[0].upper()
if mnemonic not in OPCODE:
raise ValueError(f"{addr}: 알 수 없는 명령어: {mnemonic}")
opcode = OPCODE[mnemonic]
operand = 0
if len(parts) >= 2:
arg = parts[1]
if arg in labels:
operand = labels[arg]
else:
operand = parse_number(arg)
if operand < 0 or operand > 0x0FFF:
raise ValueError(f"{addr}: operand 범위 초과 0~4095: {operand}")
word = (opcode << 12) | (operand & 0x0FFF)
machine.append(word)
return machine, labels, instructions
def main():
if len(sys.argv) != 2:
print("사용법: python asmtohex.py led.asm")
sys.exit(1)
asm_path = Path(sys.argv[1])
if not asm_path.exists():
print(f"파일 없음: {asm_path}")
sys.exit(1)
hex_path = asm_path.with_suffix(".hex")
asm_text = asm_path.read_text(encoding="utf-8")
machine, labels, instructions = assemble(asm_text)
with hex_path.open("w", encoding="utf-8") as f:
for word in machine:
f.write(f"{word:04X}\n")
print("라벨:")
for name, addr in labels.items():
print(f" {name} = {addr}")
print()
print("기계어:")
for addr, word in enumerate(machine):
print(f" {addr:02d}: {word:04X} ; {instructions[addr]}")
print()
print(f"HEX 생성 완료: {hex_path}")
if __name__ == "__main__":
main()
docs/기초실습/files/hexsend.py
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#!/usr/bin/env python3
import sys
import time
from pathlib import Path
try:
import serial
except ImportError:
print("pyserial이 필요합니다.")
print("설치: pip install pyserial")
sys.exit(1)
PORT = "COM3"
BAUD = 115200
def read_hex_file(hex_path):
data = bytearray()
for line_no, raw_line in enumerate(hex_path.read_text(encoding="utf-8").splitlines(), start=1):
line = raw_line.split(";")[0].strip()
if not line:
continue
line = line.replace("0x", "").replace("0X", "")
if len(line) != 4:
raise ValueError(f"{line_no}번째 줄 오류: 16비트 HEX 4자리여야 함: {raw_line}")
word = int(line, 16)
high = (word >> 8) & 0xFF
low = word & 0xFF
data.append(high)
data.append(low)
return data
def main():
if len(sys.argv) != 2:
print("사용법: python hexsend.py led.hex")
sys.exit(1)
hex_path = Path(sys.argv[1])
if not hex_path.exists():
print(f"파일 없음: {hex_path}")
sys.exit(1)
send_data = read_hex_file(hex_path)
send_data.append(0xFF)
send_data.append(0xFF)
print(f"파일: {hex_path}")
print(f"전송 바이트 수: {len(send_data)}")
print("전송 데이터:")
print(send_data.hex(" ").upper())
ser = serial.Serial(
port=PORT,
baudrate=BAUD,
bytesize=serial.EIGHTBITS,
parity=serial.PARITY_NONE,
stopbits=serial.STOPBITS_ONE,
timeout=1
)
time.sleep(2)
ser.reset_input_buffer()
ser.reset_output_buffer()
ser.write(send_data)
ser.flush()
ser.close()
print()
print(f"{PORT}, {BAUD}bps 전송 완료")
if __name__ == "__main__":
main()
docs/기초실습/files/led.asm
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LOAD 1 ; R0 = 5
LOOP:
LED_ON ; LED 켜기
DELAY 300 ; 대기
LED_OFF ; LED 끄기
DELAY 300 ; 대기
DEC ; R0 = R0 - 1
JNZ LOOP ; R0 != 0이면 LOOP로 이동
JZ END_ON ; R0 == 0이면 END_ON으로 이동
END_ON:
LED_ON ; LED 켠 상태 유지
JMP END_ON ; 무한 반복
docs/기초실습/files/led.hex
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1001
7000
912C
8000
912C
3000
6001
5008
7000
4008
docs/기초실습/files/micom.vhdl
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity micom is
port (
clk : in std_logic; -- 50MHz
reset : in std_logic; -- High reset
uart_rx : in std_logic;
led : out std_logic
);
end entity;
architecture rtl of micom is
constant CLK_FREQ : integer := 50000000;
constant BAUD_RATE : integer := 115200;
constant BAUD_CNT : integer := CLK_FREQ / BAUD_RATE;
type ram_type is array (0 to 255) of std_logic_vector(15 downto 0);
signal prog_ram : ram_type := (others => x"0000");
type uart_state_type is (
UART_IDLE,
UART_START,
UART_DATA,
UART_STOP
);
signal uart_state : uart_state_type := UART_IDLE;
signal baud_counter : integer range 0 to BAUD_CNT := 0;
signal bit_index : integer range 0 to 7 := 0;
signal rx_shift : std_logic_vector(7 downto 0) := (others => '0');
signal rx_byte : std_logic_vector(7 downto 0) := (others => '0');
signal rx_valid : std_logic := '0';
signal byte_high : std_logic_vector(7 downto 0) := (others => '0');
signal rx_phase : std_logic := '0';
signal wr_addr : integer range 0 to 255 := 0;
signal cpu_run : std_logic := '0';
type cpu_state_type is (
CPU_LOAD_PROGRAM,
CPU_FETCH,
CPU_DECODE,
CPU_DELAY
);
signal cpu_state : cpu_state_type := CPU_LOAD_PROGRAM;
signal pc : integer range 0 to 255 := 0;
signal inst : std_logic_vector(15 downto 0) := x"0000";
signal opcode : std_logic_vector(3 downto 0);
signal operand : unsigned(11 downto 0);
signal r0 : unsigned(15 downto 0) := (others => '0');
signal zflag : std_logic := '0';
signal delay_counter : unsigned(31 downto 0) := (others => '0');
begin
opcode <= inst(15 downto 12);
operand <= unsigned(inst(11 downto 0));
--------------------------------------------------------------------
-- UART RX
--------------------------------------------------------------------
process(clk, reset)
begin
if reset = '1' then
uart_state <= UART_IDLE;
baud_counter <= 0;
bit_index <= 0;
rx_shift <= (others => '0');
rx_byte <= (others => '0');
rx_valid <= '0';
elsif rising_edge(clk) then
rx_valid <= '0';
case uart_state is
when UART_IDLE =>
if uart_rx = '0' then
baud_counter <= BAUD_CNT / 2;
uart_state <= UART_START;
end if;
when UART_START =>
if baud_counter = 0 then
if uart_rx = '0' then
baud_counter <= BAUD_CNT - 1;
bit_index <= 0;
uart_state <= UART_DATA;
else
uart_state <= UART_IDLE;
end if;
else
baud_counter <= baud_counter - 1;
end if;
when UART_DATA =>
if baud_counter = 0 then
rx_shift(bit_index) <= uart_rx;
baud_counter <= BAUD_CNT - 1;
if bit_index = 7 then
uart_state <= UART_STOP;
else
bit_index <= bit_index + 1;
end if;
else
baud_counter <= baud_counter - 1;
end if;
when UART_STOP =>
if baud_counter = 0 then
rx_byte <= rx_shift;
rx_valid <= '1';
uart_state <= UART_IDLE;
else
baud_counter <= baud_counter - 1;
end if;
end case;
end if;
end process;
--------------------------------------------------------------------
-- Loader
-- 실행 중 새 UART 데이터가 들어오면 자동 초기화 후 재다운로드
--------------------------------------------------------------------
process(clk, reset)
variable word_data : std_logic_vector(15 downto 0);
begin
if reset = '1' then
byte_high <= (others => '0');
rx_phase <= '0';
wr_addr <= 0;
cpu_run <= '0';
elsif rising_edge(clk) then
if rx_valid = '1' then
-- CPU 실행 중 새 데이터가 들어오면 기존 실행 중지 후 재다운로드 시작
if cpu_state /= CPU_LOAD_PROGRAM then
wr_addr <= 0;
rx_phase <= '0';
cpu_run <= '0';
byte_high <= rx_byte;
rx_phase <= '1';
else
if rx_phase = '0' then
byte_high <= rx_byte;
rx_phase <= '1';
else
word_data := byte_high & rx_byte;
if word_data = x"FFFF" then
cpu_run <= '1';
rx_phase <= '0';
else
prog_ram(wr_addr) <= word_data;
if wr_addr < 255 then
wr_addr <= wr_addr + 1;
end if;
rx_phase <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- CPU
--------------------------------------------------------------------
process(clk, reset)
begin
if reset = '1' then
cpu_state <= CPU_LOAD_PROGRAM;
pc <= 0;
inst <= x"0000";
r0 <= (others => '0');
zflag <= '0';
delay_counter <= (others => '0');
led <= '0';
elsif rising_edge(clk) then
-- 실행 중 UART 데이터가 들어오면 CPU를 초기화하고 다운로드 모드로 전환
if rx_valid = '1' and cpu_state /= CPU_LOAD_PROGRAM then
cpu_state <= CPU_LOAD_PROGRAM;
pc <= 0;
inst <= x"0000";
r0 <= (others => '0');
zflag <= '0';
delay_counter <= (others => '0');
led <= '0';
else
case cpu_state is
when CPU_LOAD_PROGRAM =>
if cpu_run = '1' then
pc <= 0;
cpu_state <= CPU_FETCH;
end if;
when CPU_FETCH =>
inst <= prog_ram(pc);
if pc < 255 then
pc <= pc + 1;
end if;
cpu_state <= CPU_DECODE;
when CPU_DECODE =>
case opcode is
when x"0" =>
cpu_state <= CPU_FETCH;
when x"1" =>
r0 <= resize(operand, 16);
if operand = 0 then
zflag <= '1';
else
zflag <= '0';
end if;
cpu_state <= CPU_FETCH;
when x"2" =>
r0 <= r0 + 1;
if r0 + 1 = 0 then
zflag <= '1';
else
zflag <= '0';
end if;
cpu_state <= CPU_FETCH;
when x"3" =>
r0 <= r0 - 1;
if r0 - 1 = 0 then
zflag <= '1';
else
zflag <= '0';
end if;
cpu_state <= CPU_FETCH;
when x"4" =>
pc <= to_integer(operand(7 downto 0));
cpu_state <= CPU_FETCH;
when x"5" =>
if zflag = '1' then
pc <= to_integer(operand(7 downto 0));
end if;
cpu_state <= CPU_FETCH;
when x"6" =>
if zflag = '0' then
pc <= to_integer(operand(7 downto 0));
end if;
cpu_state <= CPU_FETCH;
when x"7" =>
led <= '1';
cpu_state <= CPU_FETCH;
when x"8" =>
led <= '0';
cpu_state <= CPU_FETCH;
when x"9" =>
delay_counter <= to_unsigned(to_integer(operand) * 50000, 32);
cpu_state <= CPU_DELAY;
when others =>
cpu_state <= CPU_FETCH;
end case;
when CPU_DELAY =>
if delay_counter = 0 then
cpu_state <= CPU_FETCH;
else
delay_counter <= delay_counter - 1;
end if;
end case;
end if;
end if;
end process;
end architecture;
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