# VHDL 코드 HDL Coder 을 이용하여 VHDL 코드를 생성한다. ## 생성된 코드 ``` library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity led_blink is port( clk : in std_logic; rst : in std_logic; key0 : in std_logic; key1 : in std_logic; key2 : in std_logic; key3 : in std_logic; led : out std_logic ); end entity; architecture rtl of led_blink is signal mode : unsigned(1 downto 0) := "00"; signal cnt : unsigned(31 downto 0) := (others=>'0'); signal period : unsigned(31 downto 0); signal led_state : std_logic := '0'; begin ------------------------------------------------------------------ -- period 결정 ------------------------------------------------------------------ process(mode) begin case mode is when "00" => period <= to_unsigned(0,32); when "01" => period <= to_unsigned(50000000,32); when "10" => period <= to_unsigned(25000000,32); when others => period <= to_unsigned(5000000,32); end case; end process; ------------------------------------------------------------------ -- 메인 상태기계 ------------------------------------------------------------------ process(clk,rst) begin if rst='1' then mode <= "00"; cnt <= (others=>'0'); led_state <= '0'; elsif rising_edge(clk) then ---------------------------------------------------------- -- mode 저장 ---------------------------------------------------------- if key0='1' then mode <= "00"; elsif key1='1' then mode <= "01"; elsif key2='1' then mode <= "10"; elsif key3='1' then mode <= "11"; end if; ---------------------------------------------------------- -- LED 생성 ---------------------------------------------------------- if mode = "00" then cnt <= (others=>'0'); led_state <= '0'; else if cnt >= period then cnt <= (others=>'0'); led_state <= not led_state; else cnt <= cnt + 1; end if; end if; end if; end process; led <= led_state; end architecture; ``` ## 핀배치 | 핀 번호 | 신호 | |---------|------| | PIN_T2 | clk | | PIN_E4 | rst | | PIN_A3 | key0 | | PIN_A5 | key1 | | PIN_A6 | key2 | | PIN_A20 | key3 | | PIN_B3 | led | ## 테스트 진행 해당 코드를 Quartus 를 이용하여 컴파일 하고, 동작 과정을 실습한다.