315 lines
10 KiB
VHDL
315 lines
10 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity micom is
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port (
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clk : in std_logic; -- 50MHz
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reset : in std_logic; -- High reset
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uart_rx : in std_logic;
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led : out std_logic
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);
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end entity;
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architecture rtl of micom is
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constant CLK_FREQ : integer := 50000000;
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constant BAUD_RATE : integer := 115200;
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constant BAUD_CNT : integer := CLK_FREQ / BAUD_RATE;
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type ram_type is array (0 to 255) of std_logic_vector(15 downto 0);
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signal prog_ram : ram_type := (others => x"0000");
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type uart_state_type is (
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UART_IDLE,
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UART_START,
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UART_DATA,
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UART_STOP
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);
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signal uart_state : uart_state_type := UART_IDLE;
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signal baud_counter : integer range 0 to BAUD_CNT := 0;
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signal bit_index : integer range 0 to 7 := 0;
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signal rx_shift : std_logic_vector(7 downto 0) := (others => '0');
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signal rx_byte : std_logic_vector(7 downto 0) := (others => '0');
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signal rx_valid : std_logic := '0';
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signal byte_high : std_logic_vector(7 downto 0) := (others => '0');
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signal rx_phase : std_logic := '0';
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signal wr_addr : integer range 0 to 255 := 0;
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signal cpu_run : std_logic := '0';
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type cpu_state_type is (
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CPU_LOAD_PROGRAM,
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CPU_FETCH,
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CPU_DECODE,
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CPU_DELAY
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);
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signal cpu_state : cpu_state_type := CPU_LOAD_PROGRAM;
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signal pc : integer range 0 to 255 := 0;
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signal inst : std_logic_vector(15 downto 0) := x"0000";
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signal opcode : std_logic_vector(3 downto 0);
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signal operand : unsigned(11 downto 0);
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signal r0 : unsigned(15 downto 0) := (others => '0');
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signal zflag : std_logic := '0';
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signal delay_counter : unsigned(31 downto 0) := (others => '0');
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begin
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opcode <= inst(15 downto 12);
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operand <= unsigned(inst(11 downto 0));
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--------------------------------------------------------------------
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-- UART RX
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--------------------------------------------------------------------
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process(clk, reset)
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begin
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if reset = '1' then
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uart_state <= UART_IDLE;
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baud_counter <= 0;
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bit_index <= 0;
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rx_shift <= (others => '0');
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rx_byte <= (others => '0');
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rx_valid <= '0';
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elsif rising_edge(clk) then
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rx_valid <= '0';
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case uart_state is
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when UART_IDLE =>
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if uart_rx = '0' then
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baud_counter <= BAUD_CNT / 2;
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uart_state <= UART_START;
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end if;
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when UART_START =>
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if baud_counter = 0 then
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if uart_rx = '0' then
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baud_counter <= BAUD_CNT - 1;
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bit_index <= 0;
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uart_state <= UART_DATA;
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else
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uart_state <= UART_IDLE;
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end if;
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else
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baud_counter <= baud_counter - 1;
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end if;
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when UART_DATA =>
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if baud_counter = 0 then
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rx_shift(bit_index) <= uart_rx;
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baud_counter <= BAUD_CNT - 1;
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if bit_index = 7 then
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uart_state <= UART_STOP;
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else
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bit_index <= bit_index + 1;
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end if;
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else
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baud_counter <= baud_counter - 1;
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end if;
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when UART_STOP =>
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if baud_counter = 0 then
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rx_byte <= rx_shift;
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rx_valid <= '1';
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uart_state <= UART_IDLE;
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else
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baud_counter <= baud_counter - 1;
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end if;
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end case;
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end if;
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end process;
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--------------------------------------------------------------------
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-- Loader
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-- 실행 중 새 UART 데이터가 들어오면 자동 초기화 후 재다운로드
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--------------------------------------------------------------------
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process(clk, reset)
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variable word_data : std_logic_vector(15 downto 0);
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begin
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if reset = '1' then
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byte_high <= (others => '0');
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rx_phase <= '0';
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wr_addr <= 0;
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cpu_run <= '0';
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elsif rising_edge(clk) then
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if rx_valid = '1' then
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-- CPU 실행 중 새 데이터가 들어오면 기존 실행 중지 후 재다운로드 시작
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if cpu_state /= CPU_LOAD_PROGRAM then
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wr_addr <= 0;
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rx_phase <= '0';
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cpu_run <= '0';
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byte_high <= rx_byte;
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rx_phase <= '1';
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else
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if rx_phase = '0' then
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byte_high <= rx_byte;
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rx_phase <= '1';
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else
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word_data := byte_high & rx_byte;
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if word_data = x"FFFF" then
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cpu_run <= '1';
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rx_phase <= '0';
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else
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prog_ram(wr_addr) <= word_data;
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if wr_addr < 255 then
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wr_addr <= wr_addr + 1;
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end if;
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rx_phase <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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--------------------------------------------------------------------
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-- CPU
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--------------------------------------------------------------------
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process(clk, reset)
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begin
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if reset = '1' then
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cpu_state <= CPU_LOAD_PROGRAM;
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pc <= 0;
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inst <= x"0000";
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r0 <= (others => '0');
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zflag <= '0';
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delay_counter <= (others => '0');
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led <= '0';
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elsif rising_edge(clk) then
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-- 실행 중 UART 데이터가 들어오면 CPU를 초기화하고 다운로드 모드로 전환
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if rx_valid = '1' and cpu_state /= CPU_LOAD_PROGRAM then
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cpu_state <= CPU_LOAD_PROGRAM;
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pc <= 0;
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inst <= x"0000";
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r0 <= (others => '0');
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zflag <= '0';
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delay_counter <= (others => '0');
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led <= '0';
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else
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case cpu_state is
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when CPU_LOAD_PROGRAM =>
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if cpu_run = '1' then
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pc <= 0;
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cpu_state <= CPU_FETCH;
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end if;
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when CPU_FETCH =>
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inst <= prog_ram(pc);
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if pc < 255 then
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pc <= pc + 1;
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end if;
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cpu_state <= CPU_DECODE;
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when CPU_DECODE =>
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case opcode is
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when x"0" =>
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cpu_state <= CPU_FETCH;
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when x"1" =>
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r0 <= resize(operand, 16);
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if operand = 0 then
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zflag <= '1';
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else
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zflag <= '0';
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end if;
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cpu_state <= CPU_FETCH;
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when x"2" =>
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r0 <= r0 + 1;
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if r0 + 1 = 0 then
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zflag <= '1';
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else
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zflag <= '0';
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end if;
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cpu_state <= CPU_FETCH;
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when x"3" =>
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r0 <= r0 - 1;
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if r0 - 1 = 0 then
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zflag <= '1';
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else
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zflag <= '0';
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end if;
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cpu_state <= CPU_FETCH;
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when x"4" =>
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pc <= to_integer(operand(7 downto 0));
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cpu_state <= CPU_FETCH;
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when x"5" =>
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if zflag = '1' then
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pc <= to_integer(operand(7 downto 0));
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end if;
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cpu_state <= CPU_FETCH;
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when x"6" =>
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if zflag = '0' then
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pc <= to_integer(operand(7 downto 0));
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end if;
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cpu_state <= CPU_FETCH;
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when x"7" =>
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led <= '1';
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cpu_state <= CPU_FETCH;
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when x"8" =>
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led <= '0';
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cpu_state <= CPU_FETCH;
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when x"9" =>
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delay_counter <= to_unsigned(to_integer(operand) * 50000, 32);
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cpu_state <= CPU_DELAY;
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when others =>
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cpu_state <= CPU_FETCH;
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end case;
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when CPU_DELAY =>
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if delay_counter = 0 then
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cpu_state <= CPU_FETCH;
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else
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delay_counter <= delay_counter - 1;
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end if;
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end case;
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end if;
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end if;
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end process;
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end architecture; |